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XE1203F
sck
si
A(4)
A(3)
A(2)
A(1)
A(0)
D(7)
/en
so
High impedance
Figure 13: Write sequence into configuration register at address zero
The time diagram of a read sequence is illustrated in Figure 14 below. The sequence is initiated when a Start
condition is detected, defined by the SI signal being set to “0” during a period of SCK. The next bit is a read/write
(R/W) bit which should be “1” to indicate a read operation. The next 5 bits are the address of the control register
A[4:0] to be accessed, MSB first. The data from the register is then output on the SO pin. The data become valid at
the rising edges of SCK and should be sampled at the falling edge of SCK. After this, the data transfer is
terminated. The SI line must stay high for at least one extra SCK clock cycle to start a new write or read sequence.
The maximum current drive on SO is 2 mA at a supply voltage of 2.7V and the maximum load is CLop, as defined
in Paragraph 3.2.2.
When the serial interface is not used for read or write operations, both SCK and SI should be set to “1”. Except
when in read mode, SO is set to a high impedance mode.
sck
si
A(4)
A(3)
A(2) A(1)
A(0)
/en
so
High impedance
D(7) D(6) D(5)
D(4) D(3)
D(2) D(1)
D(0) High impedance
Figure 14: Read sequence of configuration register
When reading the register at address zero, the timing diagram is illustrated in Figure 15.
? Semtech 2008
19
www.semtech.com
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